Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)2 product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and This paper was presented in part at the IEEE workshop on Signal Processing Systems, October 8–10, Washington, D.C. Metro Area, U.S.A, 2008. C. Leroux (B) · C. Jego · P. Adde · D. Gupta · M. Jezequel Institut TELECOM, TELECOM Bretagne, CNRS Lab-STICC, UMR 3192, Université Européenne de Bretagne, Technopôle Brest-Iroise, 83818-29238 Brest Cedex 3, France e-mail: [email protected] C. Jego e-mail: [email protected] P. Adde e-mail: [email protected] D. Gupta e-mail: [email protected] M. Jezequel e-mail: [email protected] existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.